View MX29SL402CBXBI-90G_7838399.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b 4m-bit [512k x 8 / 256k x 16] single voltage 1.8v only flash memory features general features ? single power supply operation - 1.65 to 2.2 volt for read, erase, and program operations 524,288 x 8 / 262,144 x 16 switchable boot sector architecture - t = top boot sector - b = bottom boot sector sector structure - 16k-byte x 1, 8k-byte x 2, 32k-byte x 1, and 64k-byte x 7 sector protection - hardware method to disable any combination of sectors from program or erase operations - temporary sector unprotected allows code changes in previously locked sectors latch-up protected to 100ma from -1v to vcc + 1v compatible with jedec standard - pinout and software compatible to single power supply flash performance high performance - access time: 90ns - byte/word program time: 12us/18us (typical) - erase time: 1.3s/sector, 9s/chip (typical) low power consumption - low active read current: 6ma (maximum) at 5mhz - low standby current: 1ua (typical) typical 100,000 erase/program cycle 10 years data retention software features erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased status reply - data# polling & toggle bits provide detection of program and erase operation completion support common flash interface (cfi) hardware features ready/busy# (ry/by#) output - provides a hardware method of detecting program and erase operation completion hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode package 48-pin tsop 48-ball fbga (6x8x1.2mm, 6x8x1.3mm,4x6x0.75mm) 48-ball xflga (4x6x0.5mm) all pb-free devices are rohs compliant
2 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b pin configurations 48 tsop (standard type) (12mm x 20mm) 48-ball csp (6x8x1.2mm/6x8x1.3mm, ball pitch=0.8mm), top view, balls facing down 6 5 4 3 2 1 abcdefgh a9 we# ry/by# a7 a3 a8 re- set# nc a17 a4 a10 nc nc a6 a2 a11 nc nc a5 a1 q7 q5 q2 q0 a0 q14 q12 q10 q8 ce# q13 vcc q11 q9 oe# q6 q4 q3 q1 gnd a13 a12 a14 a15 a16 byte# q15/ a-1 gnd a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# nc a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b 48-ball csp(4x6x0.75mm, ball pitch=0.5mm), top view, balls facing down 48-ball xflga (4x6x0.5mm, land pitch=0.5mm), top view, balls facing down 6 5 4 3 2 1 ab cdef h gj a1 a0 ce# gnd kl a3 a5 q8 oe# q0 a7 nc q10 q9 q1 nc nc q2 q3 vcc q12 nc nc q13 a10 a2 a4 a6 a17 nc nc we# nc a9 a8 q4 q5 q14 a13 a11 a12 q11 q6 q15 a14 a15 a16 q7 gnd 6 5 4 3 2 1 ab cdef h gj a1 a0 ce# gnd kl a3 a5 q8 oe# q0 a7 nc q10 q9 q1 nc byte# q2 q3 vcc q12 nc nc q13 a10 a2 a4 a6 a17 nc nc we# re- set# a9 a8 q4 q5 q14 a13 a11 a12 q11 q6 q15/ a-1 a14 a15 a16 q7 gnd
4 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b pin description symbol pin name a0~a17 address input q0~q14 data input/output q15/a-1 q15 (data input/output, word mode)/ a-1(lsb address input, byte mode) ce# chip enable input we# write enable input byte# word/byte selection input reset# hardware reset pin oe# output enable input ry/by# ready/busy output vcc power supply pin (1.65v~2.2v) gnd ground pin logic symbol 16 or 8 q0-q15 (a-1) ry/by# a0-a17 ce# oe# we# reset# byte# 18
5 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-am am: msb address ce# oe# we# reset# byte#
6 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b table 1. block structure mx29sl402ct sector architecture sector sector size address range sector address byte mode word mode byte mode (x8) word mode (x16) a17 a16 a15 a14 a13 a12 sa0 64kbytes 32kwords 00000h-0ffffh 00000h-07fffh 0 0 0 x x x sa1 64kbytes 32kwords 10000h-1ffffh 08000h-0ffffh 0 0 1 x x x sa2 64kbytes 32kwords 20000h-2ffffh 10000h-17fffh 0 1 0 x x x sa3 64kbytes 32kwords 30000h-3ffffh 18000h-1ffffh 0 1 1 x x x sa4 64kbytes 32kwords 40000h-4ffffh 20000h-27fffh 1 0 0 x x x sa5 64kbytes 32kwords 50000h-5ffffh 28000h-2ffffh 1 0 1 x x x sa6 64kbytes 32kwords 60000h-6ffffh 30000h-37fffh 1 1 0 x x x sa7 32kbytes 16kwords 70000h-77fffh 38000h-3bfffh 1110x x sa8 8kbytes 4kwords 78000h-79fffh 3c000h-3cfffh 11110 0 sa9 8kbytes 4kwords 7a000h-7bfffh 3d000h-3dfffh 11110 1 sa10 16kbytes 8kwords 7c000h-7ffffh 3e000h-3ffffh 11111 x sector sector size address range sector address byte mode word mode byte mode (x8) word mode (x16) a17 a16 a15 a14 a13 a12 sa0 16kbytes 8kwords 00000h-03fffh 00000h-01fffh 00000 x sa1 8kbytes 4kwords 04000h-05fffh 02000h-02fffh 00001 0 sa2 8kbytes 4kwords 06000h-07fffh 03000h-03fffh 00001 1 sa3 32kbytes 16kwords 08000h-0ffffh 04000h-07fffh 0001x x sa4 64kbytes 32kwords 10000h-1ffffh 08000h-0ffffh 0 0 1 x x x sa5 64kbytes 32kwords 20000h-2ffffh 10000h-17fffh 0 1 0 x x x sa6 64kbytes 32kwords 30000h-3ffffh 18000h-1ffffh 0 1 1 x x x sa7 64kbytes 32kwords 40000h-4ffffh 20000h-27fffh 1 0 0 x x x sa8 64kbytes 32kwords 50000h-5ffffh 28000h-2ffffh 1 0 1 x x x sa9 64kbytes 32kwords 60000h-6ffffh 30000h-37fffh 1 1 0 x x x sa10 64kbytes 32kwords 70000h-7ffffh 38000h-3ffffh 1 1 1 x x x mx29sl402cb sector architecture
7 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b table 2. bus operation notes: 1. vhv is the very high voltage, 10v to 11v. 2. x means input high (vih) or input low (vil). 3. sa means sector address: a12~a17. 4. code=00h/xx00h means unprotected. code=01h/xx01h means protected. address description ce# oe# we# reset# a17 a11 a9 a8 a6 a5 a1 a0 q0~q7 byte# byte#=vil a12 a10 read l l h h ain dout dout q8~q14 =high z a-1 x vhv vhv vhv vhv x x x l l x write l h l h ain reset x x x l x high z high z high z temporary sector unprotection output disable l h h h x high z high z high z standby vcc x x vcc x high z high z high z 0.3v 0.3v sector protect l h l chip unprotected l h l sector protection verify l l h h sa x =vih q8~q14 q15/a-1 q8~q15 xxx ain din din high z x l x h l code(4) x x sa x x x l x h l din x x xxxxhxhl din x x a7 a2 din din
8 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b requirements for reading array data read array action is to read the data stored in the array out. while the memory device is in powered up or has been reset, it will automatically enter the status of read array. if the microprocessor wants to read the data stored in the array, it has to drive ce# (device enable control pin) and oe# (output control pin) as vil, and input the address of the data to be read into address pin at the same time. after a period of read cycle (tce or taa), the data being read out will be displayed on output pin for microprocessor to access. if ce# or oe# is vih, the output will be in tri-state, and there will be no data displayed on output pin at all. after the memory device completes embedded operation (automatic erase or program), it will automatically return to the status of read array, and the device can read the data in any address in the array. in the process of erasing, if the device receives the erase suspend command, erase operation will be stopped after a period of time no more than tready1 and the device will return to the status of read array. at this time, the device can read the data stored in any address except the sector being erased in the array. in the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. the device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. in program or erase operation, the programming or erasing failure causes q5 to go high. 2. the device is in auto select mode or cfi mode. in the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. write commands/command sequences to write a command to the device, system must drive we# and ce# to vil, and oe# to vih. in a command cycle, all address are latched at the later falling edge of ce# and we#, and all data are latched at the earlier rising edge of ce# and we#. figure 1 illustrates the ac timing waveform of a write command, and table 3 defines all the valid command sets of the device. system is not allowed to write invalid commands not defined in this datasheet. writing an invalid command will bring the device to an undefined state. reset# operation driving reset# pin low for a period more than trp will reset the device back to read mode. if the device is in program or erase operation, the reset operation will take at most a period of tready1 for the device to return to read array mode. before the device returns to read array mode, the ry/by# pin remains low (busy status). when reset# pin is held at gnd 0.3v, the device consumes standby current(isb).however, device draws larger current if reset# pin is held at vil but not within gnd 0.3v. it is recommended that the system to tie its reset signal to reset# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory.
9 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b sector protect operation when a sector is protected, program or erase operation will be disabled on these sectors. mx29sl402c t/b provides two methods for sector protection. once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting reset# pin at vhv. refer to temporary sector unprotect operation for further details. the first method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for the algorithm for this method. the other method is asserting vhv on a9 and oe# pins, with a6 and ce# at vil. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. chip unprotect operation mx29sl402c t/b provides two methods for chip unprotect. the chip unprotect operation unprotects all sectors within the device. it is recommended to protect all sectors before activating chip unprotect mode. all sectors are unprotected when shipped from the factory. the first method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for algorithm of the operation. the other method is asserting vhv on a9 and oe# pins, with a6 at vih and ce# at vil (see table 2). the unprotect operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. temporary sector unprotect operation system can apply reset# pin at vhv to place the device in temporary unprotect mode. in this mode, previously protected sectors can be programmed or erased just as it is unprotected. the devices returns to normal operation once vhv is removed from reset# pin and previously protected sectors are again protected. automatic select operation when the device is in read array mode, erase-suspended read array mode or cfi mode, user can issue read silicon id command to enter read silicon id mode. after entering read silicon id mode, user can query several silicon ids continuously and does not need to issue read silicon id mode again. when a0 is low, device will output macronix manufacture id c2. when a0 is high, device will output device id. in read silicon id mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. another way to enter read silicon id is to apply high voltage on a9 pin with ce#, oe#, a6 and a1 at vil. while the high voltage of a9 pin is discharged, device will automatically leave read silicon id mode and go back to read array mode or erase-suspended read array mode. when a0 is low, device will output macronix manufacture id c2. when a0 is high, device will output device id.
10 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b verify sector protect status operation mx29sl402c t/b provides hardware sector protection against program and erase operation for protected sectors. the sector protect status can be read through sector protect verify command. this method requires v hv on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6 and a0 pins, and sector address on a12 to a17 pins. if the read out data is 01h, the designated sector is protected. oppositely, if the read out data is 00h, the designated sector is still not being protected. data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. besides, only after successful completion of the specified command sets will the device begin its erase or program operation. other features to protect the data from accidental alternation are described as followed. write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# a vih, or oe# at vil. power-up sequence upon power up, mx29sl402c t/b is placed in read array mode. furthermore, program or erase operation will begin only after successful completion of specified command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the first command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect.
11 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b table 3. mx29sl402c t/b command definitions notes: 1. device id: 2270h/70h for top boot sector device. 22f1h/f1h for bottom boot sector device. 2. for sector protect verify result, xx00h/00h means sector is not protected, xx01h/01h means sector has been protected. 3. sector protect command is valid during vhv at reset# pin, vih at a1 pin and vil at a0, a6 pins. the last bus cyc is for protect verify. hex word byte word byte word byte word byte 1st bus cyc addr addr xxx 555 aaa 555 aaa 555 aaa 555 aaa data data f0 aa aa aa aa aa aa aa aa 2nd bus cyc addr 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 3rd bus cyc addr 555 aaa 555 aaa 555 aaa 555 aaa data 90 90 90 90 90 90 a0 a0 4th bus cyc addr x00 x00 x01 x02 (sector) x02 (s ec tor) x04 addr addr data c2h c2h id id 00/01 00/01 data data 5th bus cyc addr data 6th bus cyc addr data program command read mode reset mode silicon id device id sector protect verify automatic select hex word byte word byte word byte w ord/byte w ord/byte 1st bus cyc addr 555 aaa 555 aaa 55 aa xxx xxx data aa aa aa aa 98 98 b0 30 2nd bus cyc addr 2aa 555 2aa 555 data 55 55 55 55 3rd bus cyc addr 555 aaa 555 aaa data 80 80 80 80 4th bus cyc addr 555 aaa 555 aaa data aa aa aa aa 5th bus cyc addr 2aa 555 2aa 555 data 55 55 55 55 6th bus cyc addr 555 aaa sector sector data 10 10 30 30 cfi read erase suspend erase resume command chip erase sector erase
12 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b reset in the following situations, executing reset command will reset device back to read array mode: among erase command sequence (before the full command set is completed) sector erase time-out period erase fail (while q5 is high) among program command sequence (before the full command set is completed, erase-suspended program in- cluded) program fail (while q5 is high, and erase-suspended program fail is included) read silicon id mode sector protect verify cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode, sector protect verify or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in program mode (not program fail) or erase mode (not erase fail), device will ignore reset com- mand. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not a sector is protected. the automatic select mode has four command cycles. the first two are unlock cycles, and followed by a specific command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic select mode and back to read array. the following table shows the identification code with corresponding address. address data (hex) r epresentation manufacturer id word x00 00c2 byte x00 c2 device id word x01 2270/22f1 to p/bottom boot sector byte x02 70/f1 to p/bottom boot sector sector protect verify word (sector address) x 02 00/01 unprotected/protected byte (sector address) x 04 00/01 unprotected/protected there is an alternative method to that shown in table 3, which is intended for eprom programmers and requires vhv on address bit a9.
13 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b automatic programming the mx29sl402c t/b can provide the user program function by the form of byte-mode or word-mode. as long as the users enter the right cycle defined in the table.3 (including 2 unlock cycles and a0h), any data user inputs will automatically be programmed into the array. once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. programming will only change the bit status from "1" to "0". that is to say, it is impossible to convert the bit status from "0" to "1" by programming. meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than tready1. when the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. with the internal write state controller, the device requires the user to write the program command and data only. the typical chip program time at room temperature of the mx29sl402c t/b is 4.8 seconds. (word-mode) when the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: status q7 q6 q5 ry/by#*2 in progress*1 q7# to ggling 0 0 finished q7 stop toggling 0 1 exceed time limit q7# to ggling 1 0 *1: the status "in progress" means both program mode and erase-suspended program mode. *2: ry/by# is an open drain output pin and should be weakly connected to vdd through a pull-up resistor. *3: when an attempt is made to program a protected sector, q7 will output its complement data or q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector.
14 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b sector erase sector erase is to erase all the data in a sector with "1" and "0" as all "1". it requires six command cycles to issue. the first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. after the sector erase command sequence is issued, there is a time- out period of 50us counted internally. during the time-out period, additional sector address and sector erase command can be written multiply. once user enters another sector erase command, the time-out period of 50us is recounted. if user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. the number of sectors could be from one sector to all sectors. after time-out period passing by, additional erase command is not accepted and erase embedded operation begins. during sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. when the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: status q7 q6 q5 q2 ry/by# in progress 0 to ggling 0 toggling 0 finished 1 stop toggling 0 1 1 exceed time limit 0 to ggling 1 toggling 0 when the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: status q7 q6 q5 q3 q2 ry/by#*2 time-out period 0 to ggling 0 0 toggling 0 in progress 0 to ggling 0 1 toggling 0 finished 1 stop toggling 0 1 1 1 exceed time limit 0 to ggling 1 1 toggling 0 chip erase chip erase is to erase all the data with "1" and "0" as all "1". it needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. during chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. after chip erase, the chip will return to the state of read array. *1: the status q3 is the time-out period indicator. when q3=0, the device is in time-out period and is acceptible to another sector address to be erased. when q3=1, the device is in erase operation and only erase suspend is valid. *2: ry/by# is open drain output pin and should be weakly connected to vdd through a pull-up resistor. *3: when an attempt is made to erase a protected sector, q7 will output its complement data or q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector.
15 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. sector erase resume sector erase resume command is valid only when the device is in erase suspend state. after erase resume, user can issue another erase suspend command, but there should be a 10ms interval between erase resume and the next erase suspend. if user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. status q7 q6 q5 q3 q2 ry/by# erase suspend read in erase suspended sector 1 1 0 0 to ggle 1 erase suspend read in non-erase suspended sector data data data data data 1 erase suspend program in non-erase suspended sector q7# to ggle 0 0 1 0 sector erase suspend during sector erasure, sector erase suspend is the only valid command. if user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase- suspended read array mode. if user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the tready1(<=20us) suspend finishes and the device will enter erase-suspended read array mode. user can judge if the device has finished erase suspend through q6, q7, and ry/ by#. after device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of taa; while reading the sector in erase-suspend mode, device will output its status. user can use q6 and q2 to judge the sector is erasing or the erase is suspended.
16 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b query command and common flash interface (cfi) mode mx29sl402c t/b features cfi mode. host system can retrieve the operating characteristics, structure and vendor- specified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by cfi mode. the device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h/aah (depending on word/byte mode) any time the device is ready to read array data. the system can read cfi information at the addresses given in table 4. a reset command is required to exit cfi mode and go back to ready array mode or erase suspend mode. the system can write the cfi query command only when the device is in read mode, erase suspend, standby mode or automatic select mode.. table 4-1. cfi mode: identification data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) query-unique ascii string "qry" 20 10 0051 22 11 0052 24 12 0059 primary vendor command set and control interface id code 26 13 0002 28 14 0000 address for primary algorithm extended query table 2a 15 0040 2c 16 0000 alternate vendor command set and control interface id code (none) 2e 17 0000 30 18 0000 address for secondary algorithm extended query table (none) 32 19 0000 34 1a 0000 table 4-2. cfi mode: system interface data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) vcc supply, minimum (1.65v) 36 1b 0016 vcc supply, maximum (2.2v) 38 1c 0022 vpp supply, minimum (none) 3a 1d 0000 vpp supply, maximum (none) 3c 1e 0000 typical timeout for single word/byte write (2 n us) 3e 1f 0004 typical timeout for minimum size buffer write (2 n us) 40 20 0000 typical timeout for individual block erase (2 n ms) 42 21 000a typical timeout for full chip erase (2 n ms) 44 22 0000 maximum timeout for single word/byte write times (2 n x typ) 46 23 0005 maximum timeout for buffer write times (2 n x typ) 48 24 0000 maximum timeout for individual block erase times (2 n x typ) 4a 25 0004 maximum timeout for full chip erase times (not supported) 4c 26 0000
17 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b table 4-3. cfi mode: device geometry data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) device size (2 n bytes) 4e 27 0013 flash device interface code (refer to the cfi publication 100) 50 28 0002 52 29 0000 maximum number of bytes in multi-byte write (not supported) 54 2a 0000 56 2b 0000 number of erase block regions 58 2c 0004 index for erase bank area 1 (refer to the cfi publication 100) 5a 2d 0000 5c 2e 0000 5e 2f 0040 60 30 0000 index for erase bank area 2 62 31 0001 64 32 0000 66 33 0020 68 34 0000 index for erase bank area 3 6a 35 0000 6c 36 0000 6e 37 0080 70 38 0000 index for erase bank area 4 72 39 0006 74 3a 0000 76 3b 0000 78 3c 0001 table 4-4. cfi mode: primary vendor-specific extended query data values (all values in these tables are in hexadecimal) description address address data (byte mode) (word mode) query - primary extended table, unique ascii string, pri 80 40 0050 82 41 0052 84 42 0049 major version number, ascii 86 43 0031 minor version number, ascii 88 44 0030 unlock recognizes address (0= recognize, 1= don't recognize) 8a 45 0000 erase suspend (2= to both read and program) 8c 46 0002 sector protect (n= # of sectors/group) 8e 47 0001 temporary sector unprotected (1=supported) 90 48 0001 sector protect/unprotected scheme 92 49 0004 simultaneous r/w operation (0=not supported) 94 4a 0000 burst mode (0=not supported) 96 4b 0000 page mode (0=not supported) 98 4c 0000
18 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b absolute maximum stress ratings surrounding temperature with bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 o c to +125 o c storage temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 o c to +150 o c voltage range vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +3.0 v reset#, a9 and oe# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +11.5 v the other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to vcc +0.5 v output short circuit current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 ma operating temperature and voltage industrial (i) grade surrounding temperature (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to +85 c v cc supply voltages v cc range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65v to 2.2v
19 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b dc characteristics symbol description min typ max remark iilk input leak 1.0ua iilk9 a9, oe#, reset# 35ua a9, oe#, input leak reset#=11v iolk output leak 1.0ua icr1 read current(10mhz) 12ma ce#=vil, oe#=vih icr2 read current(5mhz) 6ma ce#=vil, oe#=vih icw write current 15ma 25ma ce#=vil, oe#=vih, we#=vil isb standby current 1ua 5ua vcc=vcc max, other pin disable isbr reset current 1ua 5ua vcc=vccmax, reset# enable, other pin disable isbs sleep mode current 1ua 5ua vil input low voltage -0.5v 0.2 x vcc vih input high voltage 0.7xvcc vcc+0.3v vhv very high voltage for hardware 10v 10.5v 11v protect/unprotect/ auto select/temporary unprotect vol output low voltage 0.25v io l=2ma, vcc=vcc min 0.1v iol=100ua, vcc=vcc min voh1 ouput high voltage (ttl) 0.85xvcc ioh1=-2ma voh2 ouput high voltage (cmos) vcc-0.4v ioh2=-100ua notes: when address is not changed and remain stable for taa + 30ns, the device automatically enter auto sleep mode.
20 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b switching test circuits test condition output load : 1 ttl gate output load capacitance,cl : 30pf rise/fall times : 5ns input/output reference levels :vcc/2 switching test waveforms r1=6.2k ohm r2=2.7k ohm tested device diodes=in3064 or equivalent cl r1 vcc 0.1uf r2 vcc test points vcc 0.0v output input
21 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b ac characteristics symbol description min typ max unit taa valid data output after address 90 ns tce valid data output after ce# low 90 ns toe valid data output after oe# low 35 ns tdf data output floating after oe# high 30 ns toh data hold time after address rising 0 ns trc read period time 90 ns twc write period time 90 ns tcwc command write period time 90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 45 ns tdh data hold time 0 ns tvcs vcc setup time 50 us tcs ce# setup time 0 ns tch ce# hold time 0 ns toes oe# setup time 0 ns toeh read 0 ns toeh oe# hold time to ggle & 10 ns data# polling tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 45 ns tceph ce# pulse width high 30 ns twp we# pulse width 45 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write 0 ns twhwh1 program oper ation byte 12 us twhwh1 program oper ation word 18 us twhwh2 sector erase operation 1.3 sec tbal sector add load time 50 us
22 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 1. command write operation addresses ce# oe# we# din tds ta h data tdh tcs tch tcwc twph tw p toes ta s vih vil vih vil vih vil vih vil vih vil va va: valid address
23 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b read/reset operation figure 2. read timing waveforms addresses ce# oe# ta a we# vih vil vih vil vih vil vih vil voh vol high z high z data valid to e toeh tdf tce tr c outputs to h add valid
24 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 3. reset# timing waveform ac characteristics item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 200 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) max 20 us to read or write tready2 reset# pin low (not during automatic max 500 ns algorithms) to read or write tr h trb1 tr p 2 tr p 1 tready2 tready1 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset#
25 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b erase/program operation figure 4. automatic chip erase timing waveform tw c address oe# ce# 55h 2aah sa 10h in progress complete va va ta s ta h sa: 555h for chip erase tghwl tch tw p tds tdh read status last 2 erase command cycle tbusy tr b tcs twph we# data ry/by#
26 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed
27 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 6. automatic sector erase timing waveform tw c address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n ta s ta h tbal tghwl tch tw p tds tdh twhwh2 read status last 2 erase command cycle tbusy tr b tcs twph we# data ry/by# 30h
28 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase yes yes no data=ffh
29 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
30 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 9. automatic program timing waveforms address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tch tw p tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tbusy tr b tcs twph we# data ry/by#
31 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 10. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcep tds tdh twhwh1 or twhwh2 tbusy tr b tceph we# data ry/by#
32 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 11. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last word to be programed no no
33 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b sector protect/chip unprotect figure 12. sector protect/chip unprotect waveform (reset# control) 150us: sector protect 15ms: chip unprotect 1us vhv vih data sa, a6 a1, a0 ce# we# oe# va va va status va: valid address 40h 60h 60h verification reset#
34 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 13-1. in-system sector protect with reset#=vhv start retry count=0 reset#=vhv wait 1us write sector address with [a6,a1,a0]:[0,1,0] data: 60h write sector address with [a6,a1,a0]:[0,1,0] data: 40h read at sector address with [a6,a1,a0]:[0,1,0] wait 150us reset plscnt=1 temporary unprotect mode reset#=vih write reset cmd sector protect done device fail temporary unprotect mode retry count +1 first cmd=60h? data=01h? retry count=25? ye s ye s ye s ye s no no no no protect another sector?
35 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 13-2. chip unprotect algorithms with reset#=vhv write [a6,a1,a0]:[1,1,0] data: 60h write [a6,a1,a0]:[1,1,0] data: 40h read [a6,a1,a0]:[1,1,0] wait 15ms temporary unprotect write reset cmd chip unprotect done retry count +1 device fail all sectors protected? data=00h? retry count=1000? ye s ye s no no ye s protect all sectors start retry count=0 reset#=vhv wait 1us temporary unprotect first cmd=60h? ye s no no
36 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 14. sector protect timing waveform (a9, oe# control) notes: tvlht (voltage transition time)=4us min. twpp1 (write pulse width for sector protect)=100ns min, 10us(typ.) twpp2 (write pulse width for chip unprotected)=100ns min, 12ms(typ.) toesp (oe# setup time to we# active)=4us min. to e data oe# we# 10.5v 1.8v 10.5v 1.8v ce# a9 a1 a6 toesp twpp1 tvlht tvlht tvlht verify 01h f0h a17-a12 sector address
37 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 15. sector protection algorithm (a9, oe# control) start write sector addr retry count=0 retry count+1 sector protect done data=01h? ye s . oe#=vhv, a9=vhv, ce#=vil a6=vil activate we# pulse time out 150us we#=vih, ce#=oe#=vil a9=vhv read at sector address with a1=1 protect another sector? remove vhv from a9 write reset command device failed plscnt=32? ye s no no
38 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 16. timing waveform for chip unprotection (a9, oe# control) notes: tvlht (voltage transition time)=4us min. twpp1 (write pulse width for sector protect)=100ns min, 10us(typ.) twpp2 (write pulse width for chip unprotected)=100ns min, 12ms(typ.) toesp (oe# setup time to we# active)=4us min. to e data we# 10.5v vcc ce# a9 a1 toesp twpp2 oe# 10.5v vcc tvlht tvlht verify 00h a6 sector address a17-a12 f0h tvlht
39 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 17. chip unprotection algorithm (a9, oe# control) start protect all sectors retry count=0 chip unprotect done data=00h? ye s oe#=a9=vhv ce#=vil, a6=vih activate we# pulse time out 50ms sector protect verify from first sector with ce#=oe#=vil, a9=vhv, a1=1 all sectors have been verified? remove vhv from a9 write reset command device failed plscnt=1000? no retry count +1 no ye s ye s no go to next sector * before chip unprotect, all sectors should be protected.
40 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 18. temporary sector unprotect waveforms table 5. temporary sector unprotect parameter alt description condition speed unit trpvhh tvidr reset# rise time to vhv and vhv fall time to reset# min 500 ns tvhhwl trsp reset# vhv to we# low min 4 us reset# ce# we# ry/by# trpvhh 10.5v vhv 0 or 1.8v vil or vih tvhhwl trpvhh program or erase command sequence
41 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 19. temporary sector unprotect flowchart notes: 1. temporary unprotect all protected sectors vhv=10~11v. 2. after leaving temporary unprotect mode, the previously protected sectors are again protected. start apply reset# pin vhv volt enter program or erase mode (1) remove vhv volt from reset# (2) reset# = vih completed temporary sector unprotected mode mode operation completed
42 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 20. silicon id read timing waveform ta a tce ta a to e to h to h tdf data out c2h 70h (top boot) f1h (bottom boot) vhv vih vil a9 add ce# a1 oe# we# a0 data out data q0-q7 vih vil vih vil vih vil vih vil vih vil vih vil vih vil
43 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b write operation status figure 21. data# polling timing waveforms (during automatic algorithms) tdf tce tch to e toeh to h ce# oe# we# q7 q0-q6 ry/by# tbusy status data status data status data complement true valid data ta a tr c address va va high z high z valid data tr u e
44 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 22. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
45 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 23. toggle bit timing waveforms (during automatic algorithms) tdf tce tch to e toeh ta a tr c to h address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va notes: 1. va : valid address 2. ce# must be toggled when toggle bit toggling. va valid data
46 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 24. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 twice q5 = 1? read q7~q0 twice program/erase fail write reset cmd program/erase complete q6 toggle ? q6 toggle ? no (note1) (note1, 2) yes no no yes yes start
47 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 25. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ac characteristics word/byte configuration (byte#) parameter description speed unit -90 telfl/telfh ce# to byte# switching low/high max 5 ns tflqz byte# from l to output high-z max 30 ns tfhqv byte# from h to output active min 90 ns tfhqv telfh dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q0~q14 q15/a-1
48 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b figure 26. byte# timing waveform for read operations (byte# switching from word mode to byte mode) figure 27. byte# timing waveform for program operations ta s ta h the last we# signal (falling edge) ce# we# byte# tflqz telfl dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q0~q14 q15/a-1
49 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tr toe tf tr
50 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b latch-up characteristics erase and programming performance parameter symbol parameter description test set typ max unit cin2 control pin capacitance vin=0 7.5 9 pf cout output capacitance vout=0 8.5 12 pf cin input capacitance vin=0 6 7.5 pf tsop pin capacitance limits parameter min. typ. max. units byte programming time 12 72 us word programming time 18 108 us sector erase time 1.3 15 sec chip erase time 9 sec chip programming time byte mode 6.3 sec word mode 4.8 sec erase/program cycles 100,000 cycles note: 1. typical condition means 25 c, 1.8v. 2. maximum condition means 85 c, 1.65v, typical 100k cycles. min. max. input voltage difference with gnd on oe#, reset#, a9 -1.0v 11v input voltage difference with gnd on all power pins, address pins, ce# and we# -1.0v 2xvcc input voltage difference with gnd on all i/o pins -1.0v vcc + 1.0v vcc current -100ma +100ma includes all pins except vcc. test conditions: vcc = 1.8v, one pin per testing
51 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b part no. access operating standby package remark time (ns) current max. (ma) current max. (ua) mx29sl402cbti-90g 90 12 5 48-pin tsop pb-free (normal type) mx29sl402ctxbi-90g 90 12 5 48-ball csp-tfbga pb-free (6x8x1.2mm, ball size:0.3mm) MX29SL402CBXBI-90G 90 12 5 48-ball csp-tfbga pb-free (6x8x1.2mm, ball size:0.3mm) mx29sl402ctxei-90g 90 12 5 48-ball csp-lfbga pb-free (6x8x1.3mm, ball size:0.4mm) mx29sl402cbxei-90g 90 12 5 48-ball csp-lfbga pb-free (6x8x1.3mm, ball size:0.4mm) mx29sl402ctxhi-90g 90 12 5 48-ball csp-wfbga pb-free (4x6x0.75mm, ball pitch:0.5mm, ball size:0.3mm) mx29sl402cbxhi-90g 90 12 5 48-ball csp-wfbga pb-free (4x6x0.75mm, ball pitch:0.5mm, ball size:0.3mm) mx29sl402ctgbi-90g 90 12 5 48-ball xflga pb-free (4x6x0.5mm, land pitch:0.5mm, land opening:0.25mm) mx29sl402cbgbi-90g 90 12 5 48-ball xflga pb-free (4x6x0.5mm, land pitch:0.5mm, land opening:0.25mm) ordering information
52 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b part name description mx 29 sl 90 c t t i g option: g: lead-free package speed: 90: 90ns temperature range: i: industrial (-40? c to 85? c) package: t: tsop xb: tfbga (6x8x1.2mm, 0.8mm ball pitch, 0.3mm ball size) xe: lfbga (6x8x1.3mm, 0.8mm ball pitch, 0.4mm ball size) xh: wfbga (4x6x0.75mm, 0.5mm ball pitch, 0.3mm ball size) gb: xflga (4x6x0.5mm, 0.5mm land pitch, 0.25mm land opening) boot block type: t: top boot b: bottom boot revision: c density & mode: 402: 4m, x8/x16 boot block type: sl: 1.8v device: 29: flash 402
53 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b package information
54 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b 48-ball csp-tfbga for mx29sl402c txbi/bxbi
55 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b 48-ball csp-lfbga for mx29sl402c txei/bxei
56 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b 48-ball csp-wfbga for mx29sl402c txhi/bxhi
57 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b
58 p/n:pm1362 rev. 1.0, jun. 13, 2008 mx29sl402c t/b revision history revision description page date 1.0 1. removed "preliminary" p1 jun/13/2008 2. modified "typical 100,000 erase/program cycle" p1, 50
mx29sl402c t/b m acronix i nternational c o., l td . headquarters macronix, int'l co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 email: sales.northamerica@macronix.com macronix japan cayman islands ltd. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. taipei office macronix, int'l co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 singapore office macronix pte. ltd. 1 marine parade central #11-03 parkway centre singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications.

▲Up To Search▲

Price & Availability of MX29SL402CBXBI-90G

	To Download MX29SL402CBXBI-90G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .